1. Field of the Invention
This invention relates to a multiplex transmission method for multiplex transmission apparatuses interconnected via a multiplex transmission line for transmitting and receiving messages, and more particularly, to a multiplex transmission method for restoring multiplex transmission apparatuses which have been set in a transmission inhibited state due to a fault.
2. Description of the Related Art
Conventional multiplex transmission methods are used in systems such as a LAN in which a plurality of multiplex transmission apparatuses (hereinafter referred to as "nodes") are interconnected via a multiplex transmission line (hereinafter referred to as "bus") constituted by a paired wire or the like.
A basic node 10 is provided as shown in FIG. 6, for example. The basic node 10 includes a communication control circuit 11 comprising a communication IC connected to a bus MB, a control circuit (hereinafter referred to as "CPU") 12 for controlling the operation of the communication control circuit 11 and the input/output of data, an input/output interface circuit (hereinafter referred to as "input/output I/F circuit") 13, and a power supply circuit 14. A switch S, a motor M and other loads L, for example, are connected to the CPU 12 of the basic node 10 via the input/output I/F circuit 13.
In addition an I/O node 20 is provided as shown in FIG. 7, for example. The I/O node includes a communication control circuit 21 comprising a communication IC connected to the bus MB, and a power supply circuit 24. The communication control circuit 21 of the I/O node 20 is connected to two switches S, a lamp R and a motor M, for example, via its input and output ports 22 and 23, and this I/O node 20 exclusively takes care of the input/output of data.
In the basic node 10, the communication control circuit 11 includes a control register (not shown) therein. In a situation where a fault has occurred in the bus MB (e.g., in a branch or bus I/F of the bus), if a transmission request flag of the control register is set by the CPU 12, the communication control circuit 11 starts to transmit a frame, but upon detecting the abnormality, it sets a transmission inhibit flag in the control register and enters a transmission inhibited state.
After detecting the setting of the transmission inhibit flag, the CPU 12 clears the transmission inhibit flag upon lapse of a predetermined time period, whereby the basic node recovers from the transmission inhibited state. Upon recovery from the transmission inhibited state, the communication control circuit 11 again starts to transmit the frame. If the fault still exists, the communication control circuit 11 repeats the aforementioned transmission inhibiting operation; on the other hand, if the fault has been mended, the communication control circuit 11 transmits the frame to the end.
The communication control circuit 21 of the I/O node 20 also includes a control register (not shown) therein. In a situation where a fault has occurred in the bus MB, if a transmission request flag is set because of a change of a value in the input port 22, the communication control circuit 21 starts to transmit a frame, but upon detecting the abnormality, it sets a transmission inhibit flag in the control register and enters the transmission inhibited state.
According to the conventional multiplex transmission method, once the I/O node 20 enters the transmission inhibited state, it cannot recover from the transmission inhibited state unless it is reset, posing a problem that the I/O node cannot be immediately restored to the network after the bus fault is mended.